Large integrated circuits typically include test circuitry to test the functionality of the integrated circuit. In one test approach, known as scan design, predetermined data sequences are scanned into various internal registers of the integrated circuit during a scan mode. The integrated circuit is then allowed to operate for one or more clock cycles, and the resulting data in the internal registers is scanned out and compared to the expected resultant data. A fault is indicated when the scanned output data and the expected data do not match. The integrated circuit can be controlled to operate in a functional mode (i.e., normal operation) and a scan mode for testing.
However, the test circuitry needed to implement the scan design occupies area, significantly increasing the cost of the integrated circuit compared to a design without the scan design capability. In very complex integrated circuits such as, for example, a microprocessor, the scan circuitry may occupy a large proportion of the total integrated circuit area. Thus, using conventional scan design schemes, the integrated circuit may be impractical to manufacture with full scan design. Moreover, some conventional scan design schemes impact the timing of the functional circuitry due to the increased number of interconnects required and the addition of circuitry in the integrated circuit's functional data paths.
For example, FIG. 1 shows a block diagram of a flip-flop 100 with scan capability that can be used in an integrated circuit with scan design. The flip-flop 101 includes, for use in the functional mode, an input lead 101 for receiving a clock signal ck and an input lead 103 for receiving a data signal d for storage in the flip-flop 100. For use in the scan mode, the flip-flop 100 includes an input lead 105 for receiving a scan clock signal sclk and an input lead 107 for receiving the scan-in signal si. The flip-flop 100 includes an input lead 109 for receiving a scan enable signal se to select between the functional mode and the scan mode. When the scan enable signal se causes the flip-flop 100 to be in the functional mode, the flip-flop 100 provides an output signal q at an output lead 111. Conversely, when the scan enable signal se causes the flip-flop 100 to be in the scan mode, the flip-flop 100 provides a scan-out signal so at an output lead 113.
Typically, the flip-flop 100 includes a multiplexer (not shown) that receives the scan enable signal se at a control terminal, causing the multiplexer to select either the data signal d or the scan-in signal si. Consequently, in a large integrated circuit containing several thousand flip-flops in the scan design, a total amount of area used to implement the multiplexers in the flip-flops becomes significant. In addition, this conventional scheme requires that the scan enable signal se be routed to every flip-flop, further increasing the area occupied by the scan circuitry. Still further, the multiplexer in each flip-flop adds delay in the functional path of the flip-flop, which generally is undesirable in an integrated circuit.